1. Technical Field
One or more embodiments of the present invention generally relate to power and performance management. In particular, certain embodiments relate to managing processing system power and performance based on utilization trends.
2. Discussion
As the use of the Internet permeates throughout society and individuals become increasingly mobile, computing systems such as servers, desktop personal computers (PCs), notebook PCs, personal digital assistants (PDAs) and wireless “smart” phones continue to grow in popularity. The demand for increased functionality has resulted in the central processing units (CPUs) of these systems becoming more and more advanced, with the number of transistors continually on the rise (and transistor gate size on the decline). Processing speeds have also reached new heights. These advances, however, have presented computing system designers and well as manufacturers with a number of challenges.
A particular challenge relates to the tradeoff between performance and power consumption. For example, while the desirability of high-speed CPUs is apparent from a performance standpoint, high frequencies generally translate into greater power consumption. Similarly, smaller transistors have been linked to greater leakage current. To deal with this phenomenon, a number of conventional approaches selectively place the CPU in various performance states, where higher performance states provide relatively high performance and high power consumption, and lower performance states provide relatively low performance and low power consumption. An example of such a technique involves scaling the clock frequency of a CPU based on performance and/or power requirements.
Traditional approaches to selecting performance states identify the appropriate setting based on the utilization of the CPU. For example, it is common to define a time quantum, where utilization is calculated from the aggregate time the CPU spends in “idle” task during the time quantum. For a given CPU, an operating system (OS) schedules tasks for the CPU to execute and when there is no task to execute the CPU executes a default task called an idle task. Idle tasks also include time spent in lower power CPU states such as halt (C1/C1E), stop-grant (C2), sleep (C3) and deep sleep (C4) as described in the Advanced Configuration and Power Interface Specification (e.g., Draft ACPI Specification, Rev. x285, June, 2004).
Unfortunately, traditional approaches fail to take into consideration utilization trends that occur within a given time quantum. Thus, if the utilization of the CPU primarily occurs near the end of the time quantum, the selected performance state may fail to satisfy a demand for the CPU that is increasing. The result could be a significant degradation in performance. Similarly, if the utilization of the CPU primarily occurs near the beginning of the time quantum, the selected performance state may fail to account for a decreasing demand for the CPU. The result could be excessive power consumption in the CPU. Simply put, conventional approaches apply an equal weight to utilization/idleness periods, regardless of when they occur within the time quantum, and may therefore provide less than optimal results.